LPCB=DISABLED, TIMEOUT=LP_LAST_XFER
SDRAMC Low Power Register
| LPCB | Low-power Configuration Bits 0 (DISABLED): The low-power feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. 1 (SELF_REFRESH): The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self-refresh mode when accessed and enters it after the access. 2 (POWER_DOWN): The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down mode when accessed and enters it after the access. 3 (DEEP_POWER_DOWN): The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. |
| PASR | Partial Array Self-refresh (only for low-power SDRAM) |
| TCSR | Temperature Compensated Self-Refresh (only for low-power SDRAM) |
| DS | Drive Strength (only for low-power SDRAM) |
| TIMEOUT | Time to Define When Low-power Mode Is Enabled 0 (LP_LAST_XFER): The SDRAMC activates the SDRAM Low-power mode immediately after the end of the last transfer. 1 (LP_LAST_XFER_64): The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after the end of the last transfer. 2 (LP_LAST_XFER_128): The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after the end of the last transfer. |